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| NCP348 Positive Overvoltage Protection Controller with Internal Low RON NMOS FET and Status FLAG The NCP348 is able to disconnect the systems from its output pin in case wrong input operating conditions are detected. The system is positive overvoltage protected up to +28 V. Due to this device using internal NMOS, no external device is necessary, reducing the system cost and the PCB area of the application board. The NCP348 is able to instantaneously disconnect the output from the input, due to integrated Low RON Power NMOS (65 mW), if the input voltage exceeds the overvoltage threshold (6.4 V) or undervoltage threshold, of 3.25 V (UVLO). At powerup (EN pin = low level), the Vout turns on 50 ms after the Vin exceeds the undervoltage threshold. The NCP348 provides a negative going flag (FLAG) output, which alerts the system that a fault has occurred. In addition, the device has ESD-protected input (15 kV Air) when bypassed with a 1.0 mF or larger capacitor. Features http://onsemi.com MARKING DIAGRAM BAIM G WDFN10 MT SUFFIX CASE 516AA BAI = Specific Device Code M = Date Code G = Pb-Free Package PIN CONNECTIONS IN GND FLAG IN IN 1 2 3 4 5 PAD2 IN (Top View) PAD1 GND 10 EN 9 8 7 6 NC NC OUT OUT * * * * * * * * * * * * * * * * * Overvoltage Protection up to 28 V On-Chip Low RDS(on) NMOS Transistor: 65 mW Internal Charge Pump Overvoltage Lockout (OVLO) Undervoltage Lockout (UVLO) Internal 50 ms Startup Delay Alert FLAG Output Shutdown EN Input Compliance to IEC61000-4-2 (Level 4) 8.0 kV (Contact) 15 kV (Air) ESD Ratings: Machine Model = B Human Body Model = 3 10 Lead WDFN 2.5x2 mm Package This is a Pb-Free Device ORDERING INFORMATION Device Package Shipping 3000 / Tape & Reel 10000 / Tape & Reel NCP348MTTBG WDFN-10 (Pb-Free) NCP348MTTXG WDFN-10 (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Applications Cell Phones Camera Phones Digital Still Cameras Personal Digital Applications MP3 Players QFN-16 (c) Semiconductor Components Industries, LLC, 2006 1 November, 2006 - Rev. 2 Publication Order Number: NCP348/D NCP348 VBat VBat D3 7011X/SM NCP1835B 3 EN CFLG 2 FAULT V2P8 VSNS 1 VCC BAT TIMER 4.7 mF VBat 1M ISEL 84 270 K GND 5 6 7 9 10 ENABLE / Microprocessor V2P8 VBat 100 nF Lithium BATTERY Wall Adapter - AC/DC 1 mF NCP348 1 IN OUT 4 IN OUT 5 IN NC 10 NC EN FLAG ENABLE / 2 Microprocessor GND 0 6 7 8 9 3 15 pF 0 Figure 1. Typical Application Circuit INPUT OUTPUT 60 mA Output Impedance = 200 k ESD Protection Core Negative Protection Charge Pump Gate Driver FLAG Delay Generator 200 kHz Power ON EN Block UVLO VREF UVLO OVLO VREF OVLO DISABLE ESD Protection 10 V LDO Oscillator EN VREG VREG ESD Protection VREF Figure 2. Functional Block Diagram http://onsemi.com 2 NCP348 PIN FUNCTION DESCRIPTION Pin No. 1 4 5 Symbol IN Function POWER Description Input Voltage Pin. This pin is connected to the power supply. The device system core is supplied by this input. A 1 mF low ESR ceramic capacitor, or larger, must be connected between this pin and GND. The three IN pins must be hardwired to common supply. Ground Fault Indication Pin. This pin allows an external system to detect a fault on IN pin. The FLAG pin goes low when input voltage exceeds OVLO threshold or drop below UVLO threshold. Since the FLAG pin is open drain functionality, an external pull up resistor to VCC must be added. Output Voltage Pin. This pin follows IN pin when "no fault" is detected. The output is disconnected from the Vin power supply when the input voltage is under the UVLO threshold or above OVLO threshold. The two OUT pins must be hardwired to common supply. No Connect No Connect Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to GND to a pull down or to a I/O pin. This pin does not have an impact on the fault detection. PAD1, under the device. See PCB recommendations page 10. Can be shorted to GND. The PAD2 is electrically connected to the internal NMOS drain and connected to Pins 4 and 5. See PCB recommendations page 10. 2 3 GND FLAG POWER OUTPUT 6 7 OUT OUTPUT 8 9 10 NC NC EN OPEN OPEN INPUT PAD1 PAD2 MAXIMUM RATINGS Rating Minimum Voltage (IN to GND) Minimum Voltage (All others to GND) Maximum Voltage (IN to GND) Maximum Voltage (All others to GND) Maximum Current (UVLO Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The RqJA is highly dependent on the PCB heat sink area (connected to pad 2). As example RqJA is 268 C/W with 30 mm2 (copper 35 mm) and 189 C/W with 400 mm2. 2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114. 3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115. http://onsemi.com 3 NCP348 ELECTRICAL CHARACTERISTICS (Min/Max limits values (-40C < TA < +85C) and Vin = +5.0 V. Typical values are TA = +25C, unless otherwise noted.) Characteristic Input Voltage Range Undervoltage Lockout Threshold (Note 4) Undervoltage Lockout Hysteresis Overvoltage Lockout Threshold (Note 4) Overvoltage Lockout Hysteresis Vin versus Vout Resistance Disable Quiescent Current Supply Quiescent Current Symbol Vin UVLO UVLOhyst OVLO OVLOhyst RDS(on) Idddis Idd Conditions - - - Vin rises up OVLO threshold - Vin = 5.0 V, EN = GND, Load connected to Vout Vin = 5.0 V, EN = 1.2 V, Load connected to Vout No load. EN = 5.0 V No load. EN = Gnd UVLO Supply Current FLAG Output Low Voltage Idduvlo Volflag VIN = 2.9 V 1.2 V < VIN < UVLO Sink 50 mA on/FLAG pin VIN > OVLO Sink 1.0 mA on FLAG pin FLAG Leakage Current EN Voltage High EN Voltage Low EN Leakage Current TIMINGS Startup Delay FLAG Going Up Delay Output Turn Off Time ton tstart toff From Vin > UVLO to Vout = 0.3 V (See Figures 3 & 7) From Vout = 0.3 V to FLAG = 1.2 V (See Figures 3 & 9) From Vin > OVLO to Vout < = 0.3 V (See Figures 4 & 8) Vin increasing from 5.0 V to 8.0 V at 3.0 V/ms Rload connected on Vout From Vin > OVLO to FLAG < = 0.4 V (See Figures 4 & 10) Vin increasing from 5.0 V to 8.0 V at 3.0 V/ms Rload connected on Vout From EN > = 1.2 V to Vout < 0.3 V Rload = 5.0 W (See Figures 5 & 12) 30 30 - 55 50 1.5 70 70 5.0 ms ms ms FLAGleak Vih Vol ENleak FLAG level = 5.0 V - - EN = 5.0 V or GND Min 1.2 3.00 20 6.00 50 - - - - - - - - 1.2 - - Typ - 3.25 50 6.4 100 65 6.0 90 170 70 20 - 1.0 - - 1.0 Max 28 3.5 100 6.8 150 120 20 150 250 100 400 400 - - 0.4 - Unit V V mV V mV mW mA mA mA mA mV mV nA V V nA Alert Delay tstop - 1.0 - ms Disable Time tdis - 1.0 5.0 ms NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature. 4. Additional UVLO and OVLO thresholds ranging from UVLO and from OVLO can be manufactured. Contact your ON Semiconductor representative for availability. http://onsemi.com 4 NCP348 TIMING DIAGRAMS Figure 4. Shutdown on Overvoltage Detection EN EN Vout Vin - (RDS(on) FLAG 1.2 V tdis I) 0.3 V FLAG Vin 1.2 V OVLO UVLO 100 ms Figure 5. Disable on EN = 1 Figure 6. FLAG Response with EN = 1 http://onsemi.com 5 NCP348 TYPICAL OPERATING CHARACTERISTICS Figure 7. Startup Vin = Ch1, Vout = Ch3 Figure 8. Output Turn Off Time Vin = Ch1, Vout = Ch2 Figure 9. FLAG Going Up Delay Vout = Ch3, FLAG = Ch2 Figure 10. Alert Delay Vout = Ch1, FLAG = Ch3 Figure 11. Initial Overvoltage Delay Vin = Ch1, Vout = Ch2, FLAG = Ch3 Figure 12. Disable Time EN = Ch1, Vout = Ch2, FLAG = Ch3 http://onsemi.com 6 NCP348 TYPICAL OPERATING CHARACTERISTICS Figure 13. Inrush Current with Cout = 100 mF, I charge = 1 A, Output Wall Adaptor Inductance 1 mH Figure 14. Output Short Circuit Figure 15. Output Short Circuit (Zoom Fig. 14) http://onsemi.com 7 NCP348 CONDITIONS IN OUT VIN > OVLO 0 < VIN < UVLO And/Or VOLTAGE DETECTION /EN = 1 Figure 16. Simplified Diagram CONDITIONS IN OUT /EN = 0 & VOLTAGE DETECTION UVLO < VIN < OVLO Figure 17. Simplified Diagram Operation The NCP348 provides overvoltage protection for positive voltage, up to 28 V. A Low RDS(on) NMOS FET protects the systems (i.e.: charger) connected on the Vout pin, against positive overvoltage. At powerup, with EN pin = low, the output is rising up 50 ms after the input overtaking undervoltage UVLO (Figure 3). The NCP348 provides a FLAG output, which alerts the system that a fault has occurred. A 50 ms additional delay, regarding available output (Figure 3) is added between output signal rising up and to FLAG signal rising up. FLAG pin is an open drain output. http://onsemi.com 8 NCP348 Vout = 0 FLAG = Low Reset Timer Vin < UVLO or Vin > OVLO Vout = 0 FLAG = Low Timer Count OVLO > Vin > UVLO T < 50 ms Timer Check T = 50 ms Reset Timer Vin < UVLO or Vin > OVLO Check Vin FLAG = Low Timer Count UVLO < Vin < OVLO EN = 1 Vout = Open Check EN EN = 0 Vout = Vin Vin < UVLO or Vin > OVLO T < 50 ms Timer Check T = 50 ms UVLO < Vin < OVLO Check EN UVLO < Vin < OVLO EN = 1 Vout = Open FLAG = High Check Vin Vin < UVLO or Vin > OVLO EN = 0 Vout = Vin FLAG = High Check Vin Figure 18. State Machine http://onsemi.com 9 NCP348 Undervoltage Lockout (UVLO) To ensure proper operation under any conditions, the device has a built-in undervoltage lockout (UVLO) circuit. During Vin positive going slope, the output remains disconnected from input until Vin voltage is below 3.25 V, plus hysteresis, nominal. The FLAG output is tied to low as long as Vin does not reach UVLO threshold. This circuit has a 50 mV hysteresis to provide noise immunity to transient condition. Additional UVLO thresholds ranging from UVLO can be manufactured. Contact your ON Semiconductor representative for availability. Overvoltage Lockout (OVLO) As example: Rload = 8.0 W, Vin = 5.0 V Typical RDS(on) = 65 mW, Iout = 618 mA Vout = 8 x 0.618 = 4.95 V NMOS losses = RDS(on) x Iout2 = 0.065 x 0.6182 = 25 mW ESD Tests To protect connected systems on Vout pin from overvoltage, the device has a built-in overvoltage lockout (OVLO) circuit. During overvoltage condition, the output remains disabled as long as the input voltage exceeds 6.4 V typical. Additional OVLO thresholds ranging from OVLO can be manufactured. Contact your ON Semiconductor representative for availability. FLAG output is tied to low until Vin is higher than OVLO. This circuit has a 100 mV hysteresis to provide noise immunity to transient conditions. FLAG Output The NCP348 input pin fully supports the IEC61000-4-2. 1.0 mF (minimum) must be connected between Vin and GND, close to the device. That means, in Air condition, Vin has a "15 kV ESD protected input. In Contact condition, Vin has "8.0 kV ESD protected input. Please refer to Figure 19 to see the IEC 61000-4-2 electrostatic discharge waveform. The NCP348 provides a FLAG output, which alerts external systems that a fault has occurred. This pin is tied to low as soon the OVLO threshold is exceeded or when the Vin level is below the UVLO threshold. When Vin level recovers normal condition, FLAG is held high, keeping in mind that an additional 50 ms delay has been added between available output and FLAG = high. The pin is an open drain output, thus a pull up resistor (typically 1 MW, minimum 10 kW) must be added to Vbat. Minimum Vbat supply must be 2.5 V. The FLAG level will always reflects Vin status, even if the device is turned off (EN = 1). EN Input Figure 19. Electrostatic Discharge Waveform PCB Recommendations To enable normal operation, the EN pin shall be forced to low or connected to ground. A high level on the pin, disconnects OUT pin from IN pin. EN does not overdrive an OVLO or UVLO fault. Internal NMOS FET The NCP348 includes an internal Low RDS(on) NMOS FET to protect the systems, connected on OUT pin, from positive overvoltage. Regarding electrical characteristics, the RDS(on), during normal operation, will create low losses on Vout pin. The NCP348 integrates a 2 amperes rated NMOS FET, and the PCB rules must be respected to properly evacuate the heat out of the silicon. The PAD1 is internally isolated from the active silicon and should preferably be connected to ground. The PAD2 of the NCP348 package is connected to the internal NMOS drain and can be used to increase the heat transfer if necessary from an applications standpoint. Depending upon the power dissipated in the application, one can either use the PCB tracks connected to Pins 4 and 5 to evacuate heat, or make profit of the PAD2 area to add extra copper surface to reduce the junction temperature (See Figure 20). Of course, in any case, this pad shall be not connected to any other potential. Figure 20 shows copper area according to RqJA and allows the design of the heat transfer plane connected to PAD2. http://onsemi.com 10 NCP348 310 290 270 1 oz Sim qJA (C/W) 250 230 210 190 175 150 0 25 50 75 100 125 150 175 200 225 250 275 300 325350 COPPER HEAT SPREADING AREA (mm2) 2 2 oz C.F. 2 oz Sim 1 1 oz C.F. Figure 20. INPUT 1 IN 4 IN 5 IN 6 OUT 7 OUT NCP348 8 NC 9 NC FLAG GND 2 3 FLAG Figure 21. Demo Board Layout OUTPUT 1 mF 25 V X5R 0603 Murata GRM188R61E105KA12D C1 C2 100 nF 50 V X7R 0805 not necessary FLAG Power 10 EN_Power EN_State 321 R3 100 k EN EN R1 1M J2 2 1 GND 2 1 F1 F2 F3 F4 R2 100 k FLAG_State Figure 22. Demo Board Schematic http://onsemi.com 11 NCP348 PACKAGE DIMENSIONS WDFN10, 2.5x2, 0.5P CASE 516AA-01 ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 D3 e E E2 G G1 K L MILLIMETERS MIN NOM 0.70 0.75 0.00 --- 0.20 REF 0.20 0.25 2.50 BSC 0.97 1.08 0.57 0.68 0.50 BSC 2.00 BSC 0.80 0.90 3.75 BSC 3.50 BSC 0.20 --- 0.20 0.30 MAX 0.80 0.05 0.30 1.18 0.78 1.00 --- 0.40 PIN ONE REFERENCE 2X E 0.10 C 2X 0.10 C 0.10 C 10X 0.08 C 0.10 C A 0.05 C 10X D2 L 1 5 8X e B G 0.10 C A 0.05 C ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative III III A3 A1 B G1 D3 K 10 6 A C SEATING PLANE SOLDERING FOOTPRINT* 2.50 0.95 10X 0.58 E2 1.13 10X 0.60 0.50 PITCH b 10X 0.10 C A 0.05 C B 0.05 NOTE 3 1.45 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 12 NCP348/D |
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